As the dimensions of transistors are scaled down, the reduction of vertical junction depth and the suppression of dopant lateral diffusion, in order to control short-channel effects, become greater challenges. MOS devices have become so small that the diffusion of impurities from lightly doped source/drain (LDD) regions and source/drain regions will significantly affect the characteristics of the MOS devices. Particularly, impurities from LDD regions are readily diffused into the channel region, causing short channel effects and leakage currents between the source and drain regions.
Typically, when LDD regions are formed in a semiconductor substrate by ion implantation, the junction depth is not just dependent on the ion implant energy but can also depend on channeling and phenomena such as transient enhanced diffusion (TED) when the implanted ions migrate through the crystal lattice during subsequent thermal processing. Current techniques for forming ultra-shallow doped regions, such as p-type LDD (PLDD) regions in PMOS devices and n-type LDD (NLDD) regions in NOMS devices, use pre-amorphisation techniques to amorphise the semiconductor substrate (i.e., turn a portion of the crystalline silicon substrate into amorphous silicon) by, for example, ion implantation using non-electrically active ions, such as silicon, germanium and fluorine, in order to eliminate channeling. The pre-amorphization implantation creates in the substrate an amorphous surface layer adjacent to the underlying crystalline semiconductor material and produces a large number of defects beyond the amorphous/crystalline interface. These crystal defects are usually called End of Range (EOR) defects. Defects of this kind are known to enhance diffusion of previously implanted dopant ions during subsequent thermal processes of annealing and activation of the semiconductor device.
Methods for preventing the above-described EOR defects and controlling the diffusion of implanted dopants are thus explored.